1. Technical Field
The present invention generally relates to the processing of clock signals and, more particularly, to a programmable delay generator of equal delay steps and a cascaded interpolator.
2. Description of the Related Art
Phase rotators are critical components of clock subsystems of modern data processing and communications systems. Phase rotators are circuits that modify, in a highly precise and reproducible fashion, the phase of clock signals within an unlimited phase range and therefore are capable of generating clock signals with programmable phase and frequency offsets. A very general approach to building phase rotators is to use a two-stage circuit, where the first stage performs generation of a fixed set of clock phases that are uniformly distributed on a phase circle and/or selection of two adjacent phases from such a set, that is followed by the second stage that interpolates between the two selected phases using a high-precision interpolator circuit. The most common way to generate a set of coarse clock phases is to use a Delay Locked Loop (DLL) composed of the required number of identical delay stages, or obtain them using a divider of a higher clock frequency. Interpolation is conventionally done with current-mode logic (CML) mixers driven with current-mode digital-to-analog converters (DACs). While highly linear, CML interpolators have poor compatibility with most recent circuit designs that are predominantly of the CMOS type, i.e., of the type that employ full (rail-to-rail) signal swing and cannot directly use reduced-swing CML clocks.
One can implement an interpolator that is CMOS-compatible by using a combination of two (or more) groups of dotted CMOS tri-state inverters, with each group receiving a common input signal and all groups having one common output. The interpolation weights in this case are simply the numbers of active inverters in each group (a tristate inverter can be either fully on or off). However this method has lower linearity, and its nonlinearity increases with increases of the mutual delay of the clock phases, so it is generally limited to mutual delays of 45 degrees or less. Another disadvantage is the rigid relationship between the interpolation accuracy in bits and the number of inverters present in the circuit, the latter doubling with each extra bit of accuracy. For example, to create one output clock phase with 16 equidistant interpolated states (4 bits of accuracy) one needs at least 32 tri-state inverters for a single-ended output and 64 inverters for a dual-rail output. An immediate consequence of such use of 2^n elements to achieve n-bit accuracy is that such interpolator is natively controlled with a thermometer code. However, a thermometer code uses N−1 bits to represent N states, while binary code uses log 2(N) bits to represent N states.
The large number of coarse clock phases required by CMOS-type interpolators creates another important problem, namely skew introduced by the selection of the coarse phases from a large set, where a skew-free selection of the coarse phases from a large set is desired. However, the skew-free selection of the coarse phases from a large set is challenging due to the significant size of phase-generation circuitry and the generally non-uniform topology of such a selector.